1. Field of the Invention
The present invention relates to a synchronous delay circuit of multiplex configuration that outputs delay signals having a delay time corresponding to pulse separation immediately preceding input of the pulse signal.
2. Description of the Related Art
In a semiconductor circuit device using a clock signal, as shown in FIG. 1A, the internal clock signal 708 used in circuit 704 for clock signal control has conventionally been generated by receiving an external clock signal 701 at reception circuit 702, and amplifying at amplification circuit 703. In the process of receiving at reception circuit 702 and amplifying at amplification circuit 703, a delay time 803 was therefore generated between external clock signal 801 and internal clock signal 802, as shown in FIG. 1B. This delay time 803 has grown with the increase in circuit scale of semiconductor circuit devices accompanying developments in manufacturing technology and the increased diameters of semiconductor substrates. In addition, the circuit operation of semiconductor devices and the clock signals employed have also attained higher speeds due to the higher speeds of systems mounted in semiconductor circuit devices. Delay time 803 has consequently become relatively large with respect to clock signal cycle 804 and now presents a barrier to circuit operation.
Phase-locked loops (hereinbelow referred to as "PLL") have come into use as a countermeasure to this problem. FIG. 2 shows the basic circuit structure of a phase-locked loop. Phase comparator 901 outputs phase error signal-906 from the phase difference between external clock signal 903 inputted by way of reception circuit 902 and internal clock signal 905 inputted by way of delay circuit 904 having a delay equivalent to reception circuit 902. Phase error signal 906 passes through loop filter 907 to become control signal 908 and enters voltage-controlled oscillator 909. At voltage-controlled oscillator 909., clock signal 910 having a frequency corresponding to control signal 908 is generated. Clock signal 910 is amplified at amplification circuit 911, and becomes internal clock signal 905 used in circuit 912 for clock signal control. Phase error signal 906 and control signal 908 control voltage-controlled oscillator 909 such that the phase difference between external clock signal 903 and internal clock signal 905 is eliminated, and control voltage-controlled oscillator 909 until phase error finally cannot be detected. A PLL thus eliminates delay between the external clock signal and internal clock signal and circumvents the obstacle to circuit operation posed by the relative increase of delay time with respect to the clock signal cycle.
In semiconductor circuit devices employing a clock signal in which the duty cycle is an integer ratio or a frequency which is an integer power of the external clock signal, configurations have been used in the prior art that incorporate a frequency-dividing circuit in the PLL as shown in FIG. 3.
Delay circuit 1004 has a delay equivalent to that of reception circuit 1002. Phase comparator 1001 outputs phase error signal 1006 from the phase difference between external clock signal 1003 that has passed through reception circuit 1002 and internal clock signal 1005 that has passed through delay circuit 1004. Phase error signal 1006 passes through loop filter 1007, becomes control signal 1008, and enters voltage-controlled oscillator 1009. Voltage-controlled oscillator 1009 generates clock signal 1010 of a frequency corresponding to the voltage of control signal 1008. This clock signal 1010 is frequency-divided by frequency-divider circuit 1013, becomes clock signal 1014, is amplified at amplification circuit 1011, and becomes internal clock signal 1005 used in circuit 1012 for clock signal control. In addition, clock signal 1010 is amplified at amplification circuit 1015 and becomes internal clock signal 1016 used in circuit 1012 for clock signal control.
Phase error signal 1006 and control signal 1008 control voltage-controlled oscillator 1009 so as to eliminate the phase difference between external clock signal 1003 and internal clock signal 1005, and control voltage-controlled oscillator 1009 until phase difference finally cannot be detected.
As a result, clock signal 1005 becomes a clock signal having phase and frequency equal to that of external clock signal 1003, and moreover, having a duty cycle that is an integer ratio. In addition, clock signal 1016 has the same frequency as clock signal 1005 before frequency division, and therefore, becomes a clock signal having a frequency which is an inverse power of the frequency division of the external clock signal.
A circuit employing the above-described PLL has the following drawbacks:
1. A time interval of several tens of cycles is required before the phase difference between the internal clock signal and the external clock signal is eliminated.
2. As a result of the first drawback, the PLL must be operated constantly in order to ensure an internal clock signal having no phase difference with the external clock signal at any desired timing, thereby increasing power consumption.
3. Since the voltage-controlled oscillator controls oscillation by voltage, a decrease in the power source voltage narrows the range of the control voltage and decreases the accuracy of the control frequency.
4. Control over a broad range of frequencies while maintaining the accuracy of the fixed control frequency requires the use of a plurality of voltage-controlled oscillators of differing frequency range, and time is required to eliminate phase difference when voltage-controlled oscillators are changed.
5. The conditions for eliminating phase difference (voltage, device conditions) are limited, require investigation in advance, and this advance investigation is problematic.
6. Numerous types of circuits exist, and dealing with defects is therefore complicated.
One example of a prior-art delay circuit device directed toward solving these drawbacks is described in Japanese Patent Application No. 316875/94 and in "Synchronous Mirror Delay" ("2.5-ns clock access 250-MHz 256 Mb SDRAM with synchronous mirror delay," Takanori Saeki et al., International Solid-State Circuit Conference #23.4, 1996).
This example of a prior-art delay circuit device will be explained with reference to FIG. 4. This delay circuit device of the prior art includes: first delay circuit bank 1101 made up of a plurality of gate sections in cascade connection, that inputs and sequentially delays a signal that corresponds to the pulse signal and that parallel outputs, in order for each gate section from the input side, the output of each gate section; control circuit 1103 that parallel inputs the output of each of the gate sections of the first delay circuit bank 1101, synchronizes with the pulse 2a signal, and parallel outputs each output; second delay circuit bank 1102 made up of a plurality of gate sections in cascade connection arranged in the reverse direction of the signal transmission route of the first delay circuit bank, that parallel inputs to each gate section each output of the control circuit in the order of the gate sections from the output side, sequentially delays these inputs, and outputs the result; load adjustment element 1104; reception circuit 1105 that inputs an external signal and outputs a pulse signal;
an amplification circuit 1106; a delay circuit 1107 having a delay time equivalent to reception circuit 1105; and delay circuit 1108 having a delay time equivalent to amplification circuit 1106. In this case, the output of reception circuit 1105 is connected to the input of delay circuit 1107 and control terminal 1109. In addition, the output of delay circuit 1107 is connected to the input of delay circuit 1108, and the output of delay circuit 1108 is connected to the input of delay circuit bank 1101. The output of delay circuit bank 1102 is connected to the input of amplification, circuit 1106.
Explanation will next be given regarding the internal construction of delay circuit bank 1101, delay circuit bank 1102, control circuit 1103, and load adjustment element 1104 with reference to FIG. 5.
Delay circuit bank 1101 and delay circuit bank 1102 are made up of alternating inverters and NAND circuits. Control circuit 1103 and load adjustment element 1104 are made up of NAND circuits. Delay circuit bank 1101 is constituted by a configuration in which, from the input side, NAND circuits and inverters are connected in the order: NAND circuit FN1, inverter FI1, NAND circuit FN2, inverter FI2, . . . NAND circuit FNn, inverter FIn, NAND circuit FNn+1, inverter FIn+1, and so on. Delay circuit bank 1102 is constituted by a configuration in which, from the output side, NAND circuits and inverters are connected in the order: inverter RI1, NAND circuit RN1, inverter RI2, NAND circuit RN2, . . . inverter RIn, NAND circuit RNn, inverter RIn+1, NAND circuit RNn+1, and so on. Control circuit 1103 is composed of a NAND circuit bank NAND circuit CN1, NAND circuit CN2, . . . NAND circuit CNn, NAND circuit CNn+1, and so on, and having its one input terminal connected to control terminal 1109. Load adjustment element 1104 is composed of a NAND circuit bank NAND circuit GN1, NAND circuit GN2, . . . , NAND circuit GNn, NAND circuit GNn+1, and so on, having its one input terminal connected to ground line 1110.
Next, the mutual connections of delay circuit bank 1101, delay circuit bank 1102, control circuit 1103, and load adjustment element 1104 will be explained with respect to the (n)th element of each.
The output of inverter FIn of delay circuit bank 1101 is connected to both NAND circuit FNn+l and the input terminal of the two input terminals of NAND circuit CNn of control circuit 1103 that is not connected to control terminal 1109. The output of NAND circuit CNn of control circuit 1103 is connected both to the input terminal of the two input terminals of NAND circuit FNn+2 of delay circuit bank 1101 that is not connected to the output of inverter FIn+l, and to the input terminal of the two input terminals of NAND circuit RNn of delay circuit bank 1102 that is not connected to the output of inverter RIn+1. The output of NAND circuit RNn of delay circuit bank 1102 is connected to the input of inverter RIn of delay circuit bank 1102.
The output of inverter RIn of delay circuit bank 1102 is connected both to NAND circuit RNn-1 and to the input terminal of the two input terminals of NAND circuit GNn of load adjustment element 1104 that is not connected to ground line 1110. The output of NAND circuit GNn of load adjustment element 1104 is not connected. Power source line 1111 is connected to the input terminal of the two input terminals of NAND circuit FN1 of delay circuit bank 1101 that is not connected to the input terminal of delay circuit bank 1101, to the input terminal of the two input terminals of NAND circuit FN2 that is not connected to the output of inverter FI1, and to the input of the two inputs of the final NAND circuit of delay circuit bank 1102 that is not connected to the output of the final NAND circuit of control circuit 1103.
Next, regarding the operation of this delay circuit device of the prior art, FIG. 6 shows a waveform chart of the output waveform of the prior-art delay circuit device shown in FIG. 4.
Input clock signal 1201 is a fixed-cycle high-level pulse that uses a rising edge. Clock signal group 1202 is the output of all inverters within delay circuit bank 1101, and represents the clock signal advancing through delay circuit bank 1101. Clock signal 1203 is the output of reception circuit 1105 and represents the clock signal inputted to control terminal 1109. Clock signal group 1204 is the output of all inverters within delay circuit bank 1102 and represents the clock signals advancing through delay circuit bank 1102. Clock signal 1205 represents the output of amplification circuit 1106.
Clock signals are inputted cyclically, and in actual use, individual signals are not distinguished. However, in the interest of simplifying the explanation of operation, a single particular clock signal pulse will here be identified as the "(m)th clock signal," the next clock signal pulse will be identified as the "(m+1)th clock signal," and the next clock signal pulse will be identified as the "(m+2)th clock signal."
The (m)th clock signal, after passing through external signal reception circuit 1105, passes through delay circuit 1107 having a delay time equivalent to that of reception circuit 1105 and through delay circuit 1108 having a delay time equivalent to that of amplification circuit 1106 to enter delay circuit bank 1101, and proceeds through delay circuit bank 1101, indicated by the (m)th clock signal group within clock signal group 1202. The inverter output within delay circuit bank 1101 becomes high level due to the advance of the (m)th clock signal, and maintains high-level output during the interval of the pulse width of the (m)th clock signal. The (m+1)th clock signal is inputted from reception circuit 1105 to control terminal 1109 one clock signal cycle after the (m)th clock signal leaves reception circuit 1105 and is represented by the (m+1)th clock signal of clock signal 1203. At this time, the (m)th clock signal is advancing through delay circuit bank 1101. For example, if advances from w the (j)th inverter FIj within delay circuit bank 1101 to the (j-k)th inverter FIj-k during the width of the (m)th clock signal, the output from the (j)th inverter FIj to the (j-k)th inverter FIj-k is high level, as explained hereinabove. Accordingly, both inputs of NAND circuits CNj to CNj-k of control circuit 1103 that are connected to the output of inverters FIj to FIj-k during the progression of the (m)th clock signal are high level and their output is low level.
As a result, both inputs of the NAND circuit inputs within delay circuit bank 1102 are queued at high level. Of these, one of the two inputs of each of NAND circuits RNj to RNj-k within delay circuit bank 1102 connected to NAND circuits CNj to CNj-k of control circuit 1103 becomes low level, the output switches from high level to low level, the (m)th clock signal becomes a low-level pulse and proceeds through delay circuit bank 1102, and is represented by the (m)th clock signal group within clock signal group 1204. Of the two inputs of NAND circuits FNj+2 to FNj-k+2 within delay circuit bank 1101, the inputs that are connected to NAND circuits CNj to CNj-k of control circuit 1103 become low level, and as a result, the outputs of inverters FIj+2 to FIj-k+2 all become low level, and the (m)th clock signal within delay circuit bank 1101 is reset. The (m)th clock signal that exits delay circuit bank 1102 is outputted by way of amplification circuit 1106, and is indicated by the (m)th clock signal of clock signal 1204.
Explanation will next be presented regarding delay times. As explained hereinabove, the delay times of reception circuit 1105 and delay circuit 1107 are equal to d1. Also as explained hereinabove, the delay times of amplification circuit 1106 and delay circuit 1108 are each equal to d2. The cycle of clock signal is tCK. The delay between the rising edge of the (m)th clock signal of input clock signal 1201 and the rising edge of the (m)th clock signal of clock signal 1203 outputted from the reception circuit 1105 is d1. The delay between the (m)th clock signal of clock signal 1203 outputted from reception circuit 1105 and the rising edge of the leading clock signal of the (m)th clock signal group of clock signal group 1202 advancing through delay circuit bank 1101 is equal to the delay between the (m)th clock signal of clock signal 1203 outputted from the reception circuit 1105 and the rising edge of the (m+1)th clock signal of clock signal 1203 outputted from the reception circuit 1105, this delay being tCK. Accordingly, the time for the rising edge of the clock signal to proceed through delay circuit bank 1101 is the time interval tCK-d1-d2, or the clock signal cycle tCK less the delay times d1 and d2 of delay circuits 1107 and 1108.
The delay circuits of delay circuit bank 1102 through which the rising edge of the low-level pulse of a clock signal advances have the same number of constituent sections as the delay circuits of delay circuit bank 1101 through which the rising edge of a clock signal advances, and as a result, the time for the rising edge of a low-level pulse of a clock signal to proceed through delay circuit bank 1102 is equal to the time for the rising edge of a clock signal to proceed through delay circuit bank 1101, this value being tCK d1-d2, or the cycle of the clock signal tCK less the delay times d1 and d2 of delay circuit 1107 and 1108. As described hereinabove, the time necessary for a clock signal to pass through amplification circuit 1106 is d2. The time necessary for a clock signal to pass through reception circuit 1105, delay circuit 1107, delay circuit 1108, delay circuit bank 1101, delay circuit bank 1102, and amplification circuit 1106 is 2tCK; and the (m)th clock signal is therefore outputted to the internal circuit at the same timing as the (m+2)th clock signal.
In this example of a delay circuit device of the prior art, the delay times of delay circuit bank 1101 and delay circuit bank 1102 have been made equal, and therefore, for example, the mask patterns of NAND circuit FNn, inverter FIn, and NAND circuit CNn and the mask layouts of NAND circuit RNn, inverter RIn, and NAND circuit GNn are made mirror-image patterns and the load is equal. In addition, the power supplied this circuit may be fed from a constant-voltage supply circuit mounted on the semiconductor circuit device, and therefore, the delay times of the delay circuits do not depend on the voltage of an external power source. Moreover, by regulating the voltage supplied from the constant-voltage supply circuit, the number of gate sections used in delay circuit bank 1101 and delay circuit bank 1102 can be adjusted.
Through the use of this example of a delay circuit device of the prior art, an internal clock signal having no delay differential with the external clock signal can be obtained after a minimum of two clock signals, although the delay time differential between an external clock signal and internal clock signal is somewhat dependent on the external clock signal cycle.
In this example of a delay circuit device of the prior art, delay circuit bank 1101 and delay circuit bank 1102 are digital circuits made up of inverters and NAND circuits and the delay times of these circuits have digital values. As a result, the delay time differential of the external clock signal (the (m+2)th clock signal) and internal clock signal the output from amplification circuit 1106 of the (m)th clock signal is dependent on the cycle of the external clock signal.
Explanation will next be presented regarding this dependence of the delay time differential of the external clock signal (the (m+2)th clock signal) and the internal clock signal (the output from amplification circuit 1106 of the (m)th clock signal) on the cycles of the external clock signal.
As described in the foregoing explanation of operation, if the clock signal cycle is such that "the (m+1)th clock signal is inputted to control terminal 1109" during "the time interval that the (m)th clock signal pulse advances from the (j)th inverter FIj to the (j-k)th inverter FIj-k," the (m)th clock signal pulse "is transmitted to NAND circuits RN j to RNj-k within delay circuit bank 1102 and proceeds through delay circuit 1102," and therefore, the clock signal cycle transmitted to NAND circuits RNj to RNj-k within delay circuit bank 1102 has the width of the time interval tdF during which the (m)th clock signal advances from NAND circuit FNj to NAND circuit FNj+1. On the other hand, the delay time of the pulse advancing through delay circuit bank 1102 from NAND circuits RNj to RNj-k is fixed. As a result, when the output of first synchronous delay circuit 1100 is outputted by way of amplification circuit 1106, the dependence of the delay time differential between the amplification circuit 1106 output of the (m)th clock signal pulse and the (m+2)th external clock signal pulse upon the external clock signal cycle exhibits the sawtooth characteristic shown in FIG. 7 having a cycle which is the time to proceed from NAND circuit FNj to NAND circuit FNj+1 within delay circuit bank 1101 and having an amplitude which is the time tdB to proceed from NAND circuit RNj to NAND circuit RNj+1.
Thus, the sawtooth characteristic exhibited by the dependence of the delay time differential between the external clock signal and internal clock signal upon the cycle of the external clock signal shows a resolution corresponding to the delay times of the basic gate sections that constitute the delay circuits.